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IW4042BD manual: Quad cloced D latch, high-voltage silicon-gate CMOS
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IW4042BD Datasheet and IW4042BD manual
Manufacturer : Integral
Packing : SOIC
Pins : 16
Temperature : Min -55 °C | Max 125 °C
Size : 194 KB
Application : Quad cloced D latch, high-voltage silicon-gate CMOS
IW4042BD PDF Download